1. Field of the Invention
The present invention relates to a semiconductor memory device and method of manufacturing the same, and more particularly, to a static random access memory cell having a reduced cell size and method of manufacturing the same.
2. Discussion of Related Art
A SRAM is a significant memory device due to its high speed, low power consumption, and simple operation. The memory cell of the SRAM is constituted of flip-flop circuit. In addition, unlike a DRAM, the SRAM does not need to regularly refresh the stored data and has a straight forward design. The SRAM cell includes: two pull-up devices; two access devices; and two pull-down devices. The SRAM cell is further classified as a full CMOS cell, a high road resistor (HRL), or thin film transistor (TFT) cell according to the load types of the pull-up device.
The TFT cell utilizes P-channel TFT as the pull-up device and it is being developed in 4 Mb or 16 Mb SRAM cell. The SRAM cell with TFT cell structure has low power consumption and a good stability during a stand-by operation in contrast to the SRAM cell with HRL cell structure. In addition, it has outstanding degree of high integration in contrast to the SRAM cell with the full CMOS cell structure having a bulk structure. As the SRAM cell with TFT cell structure, however, has a complex manufacturing process, the SRAM cell with full CMOS cell structure is manufactured to a higher degree. In contrast to the SRAM cell with TFT cell structure, the SRAM cell with the full CMOS cell structure has the simple manufacturing process. In addition, the SRAM cell with the full CMOS cell structure has high current during its operation and good stability.
FIG. 1 is a conventional circuit diagram of a SRAM cell with full CMOS cell structure. In FIG. 1, WL denotes a word line, and BL1 and BL2 denote bit lines. N1 and N2 denote nodes, and VDD is a power voltage. VSS is a ground voltage. UT1 and UT2 are pull-up transistors that comprise a P-channel MOS (PMOS) transistor. DT1 and DT2 are pull-down transistors that comprise N channel MOS (NMOS) transistor. AT1 and AT2 are access transistors that comprise the NMOS transistor.
A first CMOS inverter includes the PMOS transistor for use in the pull-up transistor UT1, and the NMOS transistor for use in pull-down transistor DT1. A second CMOS inverter includes the PMOS transistor for use in the pull-up transistor UT2 and the NMOS transistor for use in the pull-down transistor DT2. An output of the first CMOS inverter is connected with an input of the second CMOS inverter at the node N1. An input of the first CMOS inverter is connected with an output of the second CMOS inverter at the node N2. The sources of the NMOS transistors for use in the access transistors AT1 and AT2, are respectively connected to the bit lines BL1 and BL2, drains of the above NMOS transistors respectively connected to the nodes N1 and N2, and gates the above NMOS transistors respectively connected to the word line WL.
In the above-described SRAM cell with full CMOS cell structure, however, its unit cell is constituted of four NMOS transistors and two PMOS transistors, so that its cell size is large. Accordingly, as the SRAM cell with full CMOS cell structure has difficulty in reducing the cell size below a predetermined level, and it is difficult to manufacture a highly integrated memory device.